ITG
The Technical Committee of Architecture for Highly
Integrated Circuits of German GI & ITG in conjunction with
ARCS 2007
March 12-15, Zürich (Switzerland)
http://arcs07.ethz.ch/
Workshop
GI

Dynamically Reconfigurable Systems (DRS)

March 15, 2007, Zürich (Switzerland)

The call for papers as PDF file
Submission deadline extended until Monday, Dec. 11

Introduction

Reconfigurable processing elements, whether used stand-alone or in conjunction with a general-purpose processor as part of an adaptive computer, have proven quite capable of providing high computational performance. By matching the processor structure to the needs of the current computation, this performance can be achieved at a much lower power consumption than with an equivalent general-purpose processor alone, and without incurring the tremendous mask and fabrication costs of a dedicated ASIC. Additional challenges, such as fault-tolerance and self-adaptation to changing environments, can also be met sucessfully using the technique of reconfiguration. It has thus been deemed the most important trend in computer and system architecture by the joint ITG/GI technical committee on the Architecture of Computing Systems (ARCS).

However, the granularity of the configuration process itself can vary between different solutions. It can occur just once, as in the case of a configurable processor whose instruction set is adapted to a specific problem domain, to occasionally, such as switching between different applications in a single system, up to dynamically, quickly altering the configuration even within a single application.

The focus of the very succesful past three Workshops on Dynamically Reconfigurable Systems (DRS) has traditionally just been the latter scenario. However, even the coarser-grained (re)configurations described above have been demonstrated as very useful in practice. Thus, for the first time, DRS is widening its scope to also address the entire spectrum of (re)configuration granularity.

We thus invite contributions dealing with problems posed by (re)configurable systems in areas such as architecture, tools, runtime systems, and middleware. Furthermore, even evaluations of applications relying on (re)configurability for their operation (and not just for prototyping!) could be suitable material. Since the entire field is still a dynamic one, do not hesitate to submit relevant work not covered by the above examples.

Workshop Topics

Deadlines

Submission until Dec. 8, 2006
Submission extended until Dec. 11, 2006
Notification of acceptance Jan. 12, 2007
Final version until Jan. 19, 2007

Submission of papers

Papers can be submitted in PDF or PostScript in English, which will also be the Workshop language.
Submission has opened. Follow this link to get to the submission site.

Formating Guidelines

The final versions of the papers shall not exceed 10 pages in VDE style (two column, a4 paper) including graphics and references.
The following material is available to assist you in producing a vaild PDF or PostScript document:

Organization

Workshop Chairs

Christian Hochberger, TU Dresden (Germany)
Andreas Koch, TU Darmstadt (Germany)

Program Committee

Mike Attig, Xilinx Research (USA)
Neil Bergmann, Queensland U of Technology (Australia)
Gordon Brebner, Xilinx Research (USA)
Jürgen Becker, University Karlsruhe (Germany)
Christophe Bobda, University Kaiserslautern (Germany)
Pedro Diniz, ST/INESC-ID, Lisbon (Portugal)
Manfred Glesner, TU Darmstadt (Germany)
Reiner Hartenstein, University Kaiserslautern (Germany)
Ulrich Heinkel, TU Chemnitz (Germany)
Andreas Herkersdorf, TU München (Germany)
Christian Hochberger, TU Dresden (Germany)
Andreas Koch, TU Darmstadt (Germany)
Rainer Kress, Infineon Technologies (Germany)
Philip Leong, Chinese University of Hong Kong (China)
Oskar Mencer, Imperial College London (UK)
Walid Najjar, University of California Riverside (USA)
Marco Platzner, University Paderborn (Germany)
Franz Josef Rammig, University Paderborn (Germany)
Wolfgang Rosenstiel, University Tübingen (Germany)
Rainer Spallek, TU Dresden (Germany)
Jürgen Teich, University Erlangen-Nuremberg (Germany)
Norbert Wehn, University Kaiserslautern (Germany)